Over the last few decades, the electronics industry has developed semiconductor technology to fabricate small, highly integrated electronic devices. Many semiconductor devices are now formed by vertical stacking of device layers, including multiple layers of conductive lines with interconnects between layers. As these devices become smaller, there is a need for increasingly narrow conductive lines and interconnects to form circuit pathways within these devices. These conductive lines and interconnects are typically formed using metals, including, for example, aluminum, tungsten, and copper.
In a multilevel architecture, layers of metal conductive lines which define circuit pathways are separated from each other by interlevel dielectrics. In a typical process, a first metal layer is deposited and patterned to form a first set of conductive lines. Deposition of a dielectric layer over the first set of conductive lines follows. Vias are etched through the dielectric layer to the underlying conductive lines and then filled with metal to establish interlayer conduction. In conventional processing methods, the metal typically extends beyond the vias when deposited. This excess metal is removed by, for example, chemical-mechanical polishing or etch back. A second metal layer may then be formed over the dielectric layer and patterned into a second set of conductive lines.
With current aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying metal-filled vias. This typically leaves at least a portion of the metal-filled vias exposed during the etch process in which the second set of conductive lines is patterned. A recess in the exposed portion of the metal-filled vias may be formed during this process. For example, if an aluminum conductive line is formed over the metal-filled via and the aluminum conductive line does not completely overlap the underlying metal-filled via, it is possible that a portion of metal-filled the via may be etched during the formation of the conductive lines. This recessing can lead to electromigration failure. Furthermore, recesses in the vias may trap chemicals or gases during subsequent processing steps. These chemicals and gases may lead to device degradation over time. In addition, the effective thinning of the via due to the presence of the recess increases the current density through that portion of the via which may lead to local overheating and electromigration. The conductive line formation typically includes one or more metal etching steps.
In an example process using a 248 nm deep ultraviolet stepper, the expected misalignment of the metal mask to the via mask is less than 0.08 .mu.m. A design rule allowing no metal-to-via overlap will result in at most 0.08 .mu.m of the aluminum alloy plug being exposed. During metal over etch, for a 0.3 .mu.m diameter via, the maximum Al plug cross-sectional area removed may be 21%. Thus, in the above example, up to one fourth of the via may be susceptible to recessing.
Tungsten is used to fill the vias in order to reduce the recess formed during subsequent processing steps. Tungsten-filled vias provide adequate selectivity during metal etching steps. However, the presence of tungsten in the path of current flow may lead to flux divergence in the metal lines at the tungsten/metal interfaces, thereby degrading the electromigration resistance.
To address this issue, aluminum, and aluminum alloys have been suggested for incorporation in the vias. In addition to reducing via resistance, aluminum vias may also show better electromigration resistance. The use of aluminum in vias is expected to become more important as the device dimensions become smaller. Conventional techniques include filling the vias with tungsten or aluminum, polishing or etching back the tungsten or aluminum to remove excess deposits outside of the via, and then depositing a second metal layer for making the conductive lines.
When aluminum is incorporated in the vias, a conventional metal etch technique cannot be used to form the conductive line, that are also typically aluminum, because the aluminum in the vias may be exposed to metal etchants which may create recessing in the vias.
One technique for reducing or eliminating the recessing of metal in the vias, particularly when the vias are formed using aluminum or an alloy thereof, involves first forming a via in a device layer of a semiconductor device, and then forming a barrier layer over the device layer. This barrier layer generally conforms to the underlying surface topology of the device layer. Following that, a metal layer is formed over the barrier layer; it also fills the via to form a via structure. A portion of the metal layer is removed. The remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. Next, a spacer is formed along the sidewall of the conductive structure. A portion of the barrier layer is removed using the spacer to protect a portion of the metal via structure adjacent the surface of the device layer. Consequently, the recessing is reduced or eliminated.
While the above technique adequately reduces or eliminates the recessing of metals for some applications, there is an ongoing need to further reduce processing and costs, and adverse impacts upon device yield. The present invention addresses the above-mentioned need and provides an improved method to prevent the formation of recesses in metal-filled vias.